1. Field of the Invention
The present invention relates to a jitter resistant clock regenerator advantegeously applicable to terminal equipment, and more particularly to a jitter resistant clock regenerator for restoring from transmitted data received on a channel a program clock signal which is used for processing program data that are defined in this specification generally as various data for use in media in an upper layer.
2. Description of the Background Art
Today, there is an increasing demand for a network system integrating multiple types of media, and its related techniques have been intensively developed. Such a network is adapted to transmit over the same channel various types of medium data, called program data hereinbelow, to be processed at different processing rates which is independent of the transmission rate of the channel.
For these program data to preferably be processed at their appropriate processing rates on a receiver site, some mechanism is required for transmitting together with the program data clock signals, called program clock signals from now on, corresponding to the processing rates of the program data, and for restoring them at the receiver site.
Thus, a method is employed which embeds timing signals in the program data at the transmitter site so that the receiver site can restore the program clock signals by extracting the timing signals from the received program data. Such a method conventionally uses a PLL (Phase-Locked Loop) circuit to align the phase of oscillation with the phase of the timing signals, thus to restore the program clock signals needed for processing the program data.
It is unavoidable, however, that jitter is involved in the transmitted data owing to transmission delay or the like encountered on the channel. Therefore, extracting the timing signals for the program data directly from the transmitted data on which the jitter is involved, and supplying the extracted timing signals to the PLL circuit may cause degradation in the accuracy of the restored program clock signals due to the timing signals momentarily fluctuated.
In view of this, it would be possible to design the lowpass filter constituting the PLL circuit so as to have its time constant increased to reduce the effect of the jitter. This, however, presents another problem of complicating the circuit and delaying the start time of the clock signal acquisition.